TK-3202/3206
9
CIRCUIT DESCRIPTION
6) Squelch
Part of the AF signal from the IC enters the FM IC (IC201)
again, and the noise component is amplified and rectified
by a filter and an amplifier to produce a DC voltage
corresponding to the noise level.
The DC signal from the FM IC goes to the analog port of
the microprocessor (IC405). IC405 determines whether to
output sounds from the speaker by checking whether the
input voltage is higher or lower than the preset value.
To output sounds from the speaker, IC405 sends a high
signal to the SP MUTE line and turns IC302 on through
Q303,Q304,Q305,Q306 and Q316. (See Fig. 4)
7) Receive Signalling
(1) QT/DQT
The output signal from FM IC (IC201) enters the
microprocessor (IC405) through IC301. IC405 determines
whether the QT or DQT matches the preset value, and
controls the SP MUTE and the speaker output sounds
according to the squelch results.
(2) MSK (Fleet Sync)
The MSK input signal from the FM IC goes to pin 31 of IC 301.
The signal is demodulated by MSK demodulator in IC 301.
The demodulated data goes to the CPU for processing.
(3) DTMF
The DTMF input signal from the FM IC (IC201) goes to
IC301, the DTMF decoder. The decoded information is then
processed by the CPU.
3. PLL Frequency Synthesizer
The PLL circuit generates the first local oscillator signal for
reception and the RF signal for transmission.
1) PLL
The frequency step of the PLL circuit is 5 or 6.25kHz.
A 12.8MHz reference an oscillator signal is divided at IC1
by a fixed counter to produce oscillator (VCO) output signal
which is buffer amplified by Q2 then divided in IC1 by a
programmable counter. The divided signal is compared in
phase with the 5 or 6.25kHz reference signal from the phase
comparator in IC1. The output signal from the phase
comparator is filtered through a low-pass filter and passed
to the VCO to control the oscillator frequency.(See Fig. 5)
2) VCO
The operating frequency is generated by Q4 in transmit
mode and Q3 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained
from the phase comparator, to the varactor diodes (D4 and
D7 in transmit mode and D5 and D9 in receive mode). The
RX pin is set high in receive mode causing Q5 turn on.
The TX pin is set high in transmit mode. The outputs from
Q3 and Q4 are amplified by Q6 and sent to the RF amplifiers.
Fig. 4 AF amplifier and squelch
RECEIVE SIGNALLING
SP
Q306,316
SW
IF Amp
FM IF IC201
IC301
IC302
AF PA
IC405
Q303,304,305
SW
QT/DQT
DTMF
CLK,DATA,
STD,LOADN
SIGNAL
AF CONT
QT/DQT IN
BUSY
CPU
AQUA
3) Unlock Detector
If a pulse signal appears at the LD pin of IC1, an unlock
condition occurs, and the DC voltage obtained from C4,
R5, and D1 causes the voltage applied to the microprocessor
to go low. When the microprocessor detects this condition,
the transmitter is disabled, ignoring the push-to-talk switch
input signal.
Fig. 5 PLL circuit
PLL DATA
X1
12.8MHz
REF OSC
1/M
1/N
PLL IC IC1
PHASE
COMPARATOR
CHARGE
PUMP
LPF
5kHz/6.25kHz
D4,7
D5,9
Q4
TX VCO
Q3
RX VCO
Q6
BUFF AMP
Q9
RF AMP
RX
TX
Q2
BUFFER
Q5, 7
T/R SW
5kHz/6.25kHz
LPF
(24 pages)
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